Unveiling the Impact of IR-Drop on Performance Gain in NCFET-Based Processors

Negative capacitance field-effect transistor (NCFET) pushes the subthreshold swing beyond its fundamental limit of 60 mV/decade by incorporating a ferroelectric material within the gate-stack of transistor. Such a material manifests itself as an NC that provides an internal voltage amplification for the transistor resulting in higher ON-current levels. Hence, the performance of processors can be boosted while the operating voltage still remains the same. However, having an NC makes the total gate terminal capacitance larger. Although the impact of that on compensating the gained performance has already been studied in the literature, this paper is the first to explore the impact of NC on exacerbating the IR-drop problem in processors. In fact, voltage fluctuation in the power delivery network (PDN) due to IR-drops is one of the prominent sources of performance loss in processors, which necessitates adding timing guardbands to sustain a reliable operation during runtime. In this paper, we study NC-FinFET standard cells and processor for the 7-nm technology node. We demonstrate that NC, on the one hand, results in larger IR-drops due to the increase in current densities across the chip, which leads to a higher stress on the PDN. However, the internal voltage amplification provided by NC, on the other hand, compensates to some degree the voltage reduction caused by IR-drop. We investigate, from physics all the way to full-chip (GDSII) level, how the overall performance of a processor is affected under the impact that NC has on magnifying and compensating IR-drop

Hardware Trojan Detection Using Controlled Circuit Aging

This paper reports a novel approach that uses transistor aging in an integrated circuit (IC) to detect hardware Trojans. When a transistor is aged, it results in delays along several paths of the IC. This increase in delay results in timing violations that reveal as timing errors at the output of the IC during its operation. We present experiments using aging-aware standard cell libraries to illustrate the usefulness of the technique in detecting hardware Trojans. Combining IC aging with over-clocking produces a pattern of bit errors at the IC output by the induced timing violations. We use machine learning to learn the bit error distribution at the output of a clean IC. We differentiate the divergence in the pattern of bit errors because of a Trojan in the IC from this baseline distribution. We simulate the golden IC and show robustness to IC-to-IC manufacturing variations. The approach is effective and can detect a Trojan even if we place it far off the critical paths. Results on benchmarks from the Trust-hub show a detection accuracy of $\geq$99%.Comment: 21 pages, 34 figure

FeFET-based Binarized Neural Networks Under Temperature-dependent Bit Errors

Ferroelectric FET (FeFET) is a highly promising emerging non-volatile memory (NVM) technology, especially for binarized neural network (BNN) inference on the low-power edge. The reliability of such devices, however, inherently depends on temperature. Hence, changes in temperature during run time manifest themselves as changes in bit error rates. In this work, we reveal the temperature-dependent bit error model of FeFET memories, evaluate its effect on BNN accuracy, and propose countermeasures. We begin on the transistor level and accurately model the impact of temperature on bit error rates of FeFET. This analysis reveals temperature-dependent asymmetric bit error rates. Afterwards, on the application level, we evaluate the impact of the temperature-dependent bit errors on the accuracy of BNNs. Under such bit errors, the BNN accuracy drops to unacceptable levels when no countermeasures are employed. We propose two countermeasures: (1) Training BNNs for bit error tolerance by injecting bit flips into the BNN data, and (2) applying a bit error rate assignment algorithm (BERA) which operates in a layer-wise manner and does not inject bit flips during training. In experiments, the BNNs, to which the countermeasures are applied to, effectively tolerate temperature-dependent bit errors for the entire range of operating temperature

Impacts of Mobility Models on RPL-Based Mobile IoT Infrastructures: An Evaluative Comparison and Survey

With the widespread use of IoT applications and the increasing trend in the number of connected smart devices, the concept of routing has become very challenging. In this regard, the IPv6 Routing Protocol for Low-power and Lossy Networks (PRL) was standardized to be adopted in IoT networks. Nevertheless, while mobile IoT domains have gained significant popularity in recent years, since RPL was fundamentally designed for stationary IoT applications, it could not well adjust with the dynamic fluctuations in mobile applications. While there have been a number of studies on tuning RPL for mobile IoT applications, but still there is a high demand for more efforts to reach a standard version of this protocol for such applications. Accordingly, in this survey, we try to conduct a precise and comprehensive experimental study on the impact of various mobility models on the performance of a mobility-aware RPL to help this process. In this regard, a complete and scrutinized survey of the mobility models has been presented to be able to fairly justify and compare the outcome results. A significant set of evaluations has been conducted via precise IoT simulation tools to monitor and compare the performance of the network and its IoT devices in mobile RPL-based IoT applications under the presence of different mobility models from different perspectives including power consumption, reliability, latency, and control packet overhead. This will pave the way for researchers in both academia and industry to be able to compare the impact of various mobility models on the functionality of RPL, and consequently to design and implement application-specific and even a standard version of this protocol, which is capable of being employed in mobile IoT applications

Instruction matching and modeling

Creating a custom processor that is application-specific is an onerous task upon a designer, who constantly has to ask whether the resulting design is optimal. To obtain such an optimal design is an NP-hard problem, made more time consuming because of the numerous combinations of available parts that make up the processor. This chapter shows two automatic methods to accelerate the process of designing ASIPs. The first method shows a formal method to match instructions that is not only fast but is also accurate. The second method shows a way to model instructions so that alternate implementations of instructions can be evaluated rapidly before being synthesized. Both these methods form part of a single design flow, which is described in the chapter. Numerous challenges remain to the rapid creation of ASIPs. These include taking power into consideration when selecting processor configurations and instructions, further reducing the time taken to match instructions by parallelizing matching algorithms, and modeling instructions in two separate steps, so that technology mapping is independently modeled, allowing models to be retargeted quickly as new standard cell libraries become available

Minimizing Excess Timing Guard Banding Under Transistor Self-Heating Through Biasing at Zero-Temperature Coefficient

Self-Heating Effects (SHE) is known as one of the key reliability challenges in FinFET and beyond. Large timing guard bands are necessary, which we try to reduce. In this work, we propose operating (biasing) processors at Zero-Temperature Coefficient (ZTC) to contain (mitigate) SHE-induced delay. Operating at ZTC allows near-zero timing guard band to protect circuits against SHE. However, a trade-off is found between thermal timing guard band and performance loss from lowering the voltage